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features ? pin-programmable mode ? supply voltage range 1.55v to 3.6v ? phy ic_usb1.0 downstream port ? bridge usb2.0 section 7 to ic_usb1.0 ? bridge ic_usb1.0 to usb2.0 section 7 ? 3.3v voltage reference ? two 70ma ldo voltage regulators ? less than 5a static current on each supply ? slew rate control to minimize radiated emi ? esd 4kv compliant with usb uicc ? applications: ? mobile usb uicc (etsi 102 600), pc usb uicc, token usb description the AT73C260 is an inter chip usb transceiver fully compliant with the universal serial bus specification, and more specifically with the ic_usb1.0 supplement. the AT73C260 is a bidirectional differential interface. the AT73C260 is ideal for applica - tions in mobile devices, pcs and usb tokens making use of an usb uicc. the AT73C260?s upstream facing port may be connected to three different interfaces: ? digital ? usb2.0 section 7 with or without cable ? ic_usb1.0 the AT73C260?s downstream port complies with ic_usb1.0. the AT73C260?s mode is selected by three pins. when pvcc is powered by 3.3v and pull down resistors are added on pdm and pdp, the AT73C260?s downstream port complies with usb2.0 section 7. the AT73C260 includes a 3.5v supply monitor, a low power band-gap, a 3.3v 70ma linear voltage regulator and a 1.8v-3.0v 70ma linear voltage regulator sim fta compliant test 27.17.2.1. the AT73C260 is specified over the industrial temperature range - 40c to +85c. the AT73C260 is available in a 3 x 3 mm, 0.5mm pitch, qfn16 package. power management and analog companions (pmaac) AT73C260 interchip usb transceiver (phy - ic_usb1.0, voltage class converter, usb2.0 - ic_usb1.0 bridges) preliminary 11030a?pmaac?13-sep-10
2 11030a?pmaac?13-sep-10 AT73C260 1. block diagram figure 1-1. AT73C260 functional block diagram 13 hvcc pvcc pdm 112 pdp 10 11 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd m<0> m<1> 14 m<2> 9 pvrf v bus vref 3.3 volt AT73C260
3 11030a?pmaac?13-sep-10 AT73C260 2. package and pinout figure 2-1. AT73C260 qfn16 package pinout - top view c260b yyww xxxxx hvcc 1 oe_n 5 hdmo 6 hdpo 7 gnd 8 vbus 4 hdm 3 hdp 2 12 pvcc 9 pvrf 10 pdm 11 pdp 16 rcv 15 m<1> 14 m<2> 13 m<0> pin 1 indicator 17 gnd thermal pad (bottom)
4 11030a?pmaac?13-sep-10 AT73C260 3. pin description table 3-1. AT73C260 pin description pin name i/o pin number type function hvcc output 1 analog host side vcc ?when pin 4 ( v bus) is grounded. the ldo on pin hvcc is in standby and its output is isolated. the host supplies hvcc with the appropriate voltage to the AT73C260?s upstream transceiver. ?when pin 4 ( v bus) is connected to a voltage source the internal voltage reference 3.3v and both ldo are activated. the ldo on pin 1 provides power at 3.3v to the AT73C260?s upstream transceiver and it may source up to 70ma. hdp i/o 2 digital bidirectional hdm i/o 3 digital bidirectional v bus input 4 analog supply, provides power to the ldos on pin 1 and 12 gnd ground 5 analog gnd ground for digital and i/os hdmo output 6 digital output hdpo output 7 digital output oe_n input 8 digital input pvrf input 9 analog pvcc ldo input reference pdm i/o 10 digital bidirectional pad pdp i/o 11 digital bidirectional pad pvcc input 12 analog peripheral side vcc ?when pin 4 ( v bus) is grounded. the ldo on pin pvcc is in standby and its output is isolated. the application supplies pvcc with the appropriate voltage to the AT73C260?s downstream transceiver. ?when pin 4 ( v bus) is connected to a voltage source, the ldo on pin pvcc follows the voltage on pin pvrf. the ldo on pin pvcc provides power to the AT73C260?s downstream transceiver and it may source up to 70ma. rcv output 13 digital output m<2> input 14 digital input. for mode configuration m<1> input 15 digital input. for mode configuration m<0> input 16 digital input. for mode configuration gnd ground 17 analog analog ground. thermal pad. shall be connected to gnd for electrical and power dissipation reasons.
5 11030a?pmaac?13-sep-10 AT73C260 4. absolute maximum ratings notes: 1. refer to power dissipation rating section) 5. recommended operating conditions note: 1. refer to power dissipation rating section 6. power dissipation ratings note: 1. according to specification jesd51-5 table 4-1. absolute maximum ratings operating temperature (industrial)..................-40c to + 85c (1) *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli - ability. storage temperature........................................-55c to + 150c power supply input on h vcc ............................... -0.3v to + 3.6v power supply input on v bus............................. -0.3v to + 5.5v digital i/o input voltage...................................... -0.3v to + 3.6v all other pins.......................................................-0.3v to + 3.6v esd (all pins)..............................................................4 kv hbm table 5-1. recommended operating conditions parameter condition min max units operating ambient temperature (1) -40 85 c power supply output p vcc 1.55 3.6 v power supply input h vcc 1.55 3.6 v power supply input v bus 4.0 5.5 v table 6-1. recommended operating conditions parameter condition min typ max units maximum junction temperature -40 -- 125 c r thja (1) package thermal junction to ambient resistance -- -- 90 c / w maximum on-chip power dissipation ambient temperature = 85c -- -- 400 mw
6 11030a?pmaac?13-sep-10 AT73C260 7. electrical characteristics 7.1 i/os dc characteristics referred to h vcc notes: 1. a 220nf ceramic capacitor is connected between the pin h vcc and the pin gnd and closest to h vcc pin. 2. r pu1 pull up resistor is as per the ecn ?pull-up/pull-down resistors? published by the usb-if. r pu1 value is between 900 and 1575 when the bus is idle and between 1425 and 3090 when the upstream device is transmitting 3. r pu2 pull up resistor is as per the ic_usb1.0 published by the usb-if. r pu2 value is between 1k and 3k to attach and between 30k and 150k during idle. 7.2 i/os dc characteristics referred to p vcc notes: 1. a 220nf ceramic capacitor is connected between the pin p vcc and the pin gnd and closest to p vcc pin. table 7-1. h vcc referred i/os: hdp, hdm, rcv, hdmo, hdpo, oe_n and m<2:0> symbol parameter comments min typ max units h vcc host side supply voltage 220nf ceramic capacitor (1) 1.55 -- 3.6 v i hvcc operating h vcc supply current full speed transceiver / receiver at 12mbps, c load = 18pf on hdp and hdm during transmit -- -- 2 ma v ih input high-level voltage v oh > v oh_min 0.65 x h vcc -- h vcc + 0.3 v v il input low-level voltage v oh < v ol_max -0.3 -- 0.35 x h vcc v v oh output high-level voltage i oh = - 2ma h vcc - 0.45 -- -- v v ol output low-level voltage i ol = 2ma -- -- 0.45 v r pdp pull-down resistors on hdp, hdm all cases 30 -- 80 k r pu1 (2) upstream pull-up resistors on hdp m<0> = 0 m<2:1> = connected to h vcc 0.9 -- 3.09 k r pu2 (3) upstream pull-up resistors on hdp m<2:0> = connected to h vcc 1 -- 150 k table 7-2. p vcc referred i/os: pdp, pdm symbol parameter comments min typ max units p vcc peripheral side supply voltage 220nf ceramic capacitor (1) 1.55 -- 3.6 v i pvcc operating p vcc supply current full speed transceiver / receiver at 12mbps, c load = 18pf on pdp and pdm during transmit -- -- 2 ma v ih input high-level voltage v oh > v oh_min 0.65 x p vcc -- p vcc + 0.3 v v il input low-level voltage v oh < v ol_max -0.3 -- 0.35 x p vcc v v oh output high-level voltage i oh = - 2ma p vcc - 0.45 -- -- v v ol output low-level voltage i ol = 2ma -- -- 0.45 v r pdh pull-down resistors all cases for pdp, pdm 30 -- 80 k
7 11030a?pmaac?13-sep-10 AT73C260 7.3 timing characteristics table notes: 1. external capacitor is a 1f or higher ceramic capacitor connected between the pin v bus and the pin gnd and closest to v bus pin 7.4 v bus supply characteristics notes: 1. external capacitor is a 1f or higher ceramic capacitor connected between the pin v bus and the pin gnd and closest to v bus pin . notes: 1. external capacitor is a 1f or higher ceramic capacitor connected between the pin v bus and the pin gnd and closest to v bus pin. table 7-3. timing table symbol parameter comments min typ max units t delay propagation delay time h vcc = 3.3v and p vcc = 3.0v -- 37 -- ns h vcc = 3.3v and p vcc = 1.8v -- 42 -- ns t slew_r_p slew rate, rise time on pdp 10%-90%, c load =33pf, p vcc =3.0v -- 5.7 -- ns 10%-90%, c load =33pf, p vcc =1.8v -- 10.5 -- t slew_r_m slew rate, rise time on pdm 10%-90%, c load =33pf, p vcc =3.0v -- 5.6 -- 10%-90%, c load =33pf, p vcc =1.8v -- 10.6 -- t slew_f_p slew rate, fall time on pdp 10%-90%, c load =33pf, p vcc =3.0v -- 6.1 -- 10%-90%, c load =33pf, p vcc =1.8v -- 7.6 -- t slew_f_m slew rate, fall time on pdm 10%-90%, c load =33pf, p vcc =3.0v -- 6.1 -- 10%-90%, c load =33pf, p vcc =1.8v -- 7.7 -- t attach attachment transit time m<2:0>=110, h vcc = 3.3v and p vcc = 3.0v -- 400 -- ns t attach attachment transit time m<2:0>=111, h vcc = 1.8v and p vcc = 3.3v -- 400 -- ns table 7-4. v bus supply monitor symbol parameter comments min typ max units v bus input supply voltage range 1f ceramic capacitor (1) 4.0 5.0 5.5 v v tp positive threshold 3.36 3.5 3.64 v v tn negative threshold 3.02 3.15 3.28 v v hys hysteresis 348 361 374 mv table 7-5. v bus current consumption symbol parameter comments min typ max units v bus input supply voltage range 1f ceramic capacitor (1) 4.0 5.0 5.5 v i vbus v bus supply current v bus active ? h vcc = 3.3v nominal ? 1.55v < p vrf < 3.6v ? loads = 0ma ? idle -- 100 150 a
8 11030a?pmaac?13-sep-10 AT73C260 7.5 h vcc and p vcc supplies characteristics 7.5.1 h vcc and p vcc current consumption 7.5.2 3.3v supplied on h vcc when v bus is greater than 3.5v nominal, an internal ldo voltage regulator provides a 3.3v nominal voltage source on pin h vcc . notes: 1. when v bus is present and greater than v tp , 10k pull down is removed on h vcc and on p vcc and ldo are started. when v bus goes below v tp , a 10k pull down is connected on h vcc and p vcc and ldo are disabled. when v bus = 0v and h vcc and p vcc within their normal range the 10k pull down are disconnected. table 7-6. p vcc and h vcc current consumption symbol parameter comments min typ max units h vcc host supply voltage 1.55 -- 3.6 v p vcc peripheral supply voltage 1.55 -- 3.6 v i vcc x vcc supply current v bus = 0v, p vrf = 0v ? loads = 0ma ? idle ? h vcc forced at 3.6v ? p vcc forced at 3.3v -- -- 5 a table 7-7. h vcc ldo characteristics symbol parameter comments min typ max units h vcc (1) output voltage - enabled when v bus is greater than 3.5v typical. - disabled when v bus goes below 3.15v typical 3.0 3.3 3.6 v i o output current 0 -- 70 ma vdd_il static load regulation ? v bus > 4.5v ? i o = 10% to 90% -- -- 10 mv dynamic load regulation ? v bus > 4.5v ? i o = 10% to 90% ? t rise = t fall = 5s -- 50 -- mv vdd_vin static line regulation ? v bus from 4.3v to 5.5v ? i o = max -- -- 20 mv ? v bus from 4.0v to 5.5v ? i o = 7 ma -- -- 20 mv t start start-up time ? v bus from 0v to 5.0v ? t rise = 10s ? i o = 0ma ? v out > 3.0v -- -- 60 s
9 11030a?pmaac?13-sep-10 AT73C260 7.5.3 voltage supplied on p vcc when v bus is greater than 3.5v nominal, an internal ldo follower provides a voltage source on pin p vcc . the voltage on pin p vcc is equal to the voltage on pin p vrf . p vcc ldo is in accordance with fta test 3gpp - 27.17.2.1 dedicated for subscriber iden - tity module (sim) application. notes: 1. when v bus is present and greater than v tp , 10k pull down is removed on h vcc and on p vcc and ldo are started. when v bus goes below v tp , a 10k pull down is connected on h vcc and p vcc and ldo are disabled. when v bus = 0v and h vcc and p vcc within their normal range the 10k pull down are disconnected. 2. off time is described in section 9.3.4 on page 16 . to reduce t stop time an external reisitor is recommended. this value depends on c out and load applied on the system. table 7-8. p vcc ldo characteristics symbol parameter comments min typ max units v bus supply input voltage on pin v bus 4.0 5.0 5.5 v p vcc (1) output voltage - enabled when v bus is greater than 3.5v typical. - disabled when v bus goes below 3.15v typical - 1.55v < p vrf < 3.6v 1.55 -- 3.6 v v off follower offset voltage p vcc - p vrf -40 -- 40 mv i o output current 0 -- 70 ma vdd_il static load regulation ? v bus > 4.5v ? i o = 10% to 90% -- -- 10 mv dynamic load regulation ? v bus > 4.5v ? i o = 10% to 90% ? t rise = t fall = 5s -- 30 -- mv vdd_vin static line regulation ? v bus from 4.3v to 5.5v ? i o = max -- -- 20 mv ? v bus from 4.0v to 5.5v ? i o = 7 ma -- -- 20 mv t start start-up time ? v bus is set at 5.0v ? p vrf 0v to 1.8v with t rise = 5s ? i o = 10ma ? v out > 1.62v -- 20 35 s ? v bus is set at 5.0v ? p vrf 0v to 3.0v with t rise = 5s ? i o = 10ma ? v out > 2.7v -- 32 50 s t stop (2) power-off time ? v bus is set at 5.0v ? p vrf 3.0v to 0v with t fall = 5s ? r load = 1k . c out =220nf/ x5r ? v out < 0.4v -- -- 525 s ? v bus is set at 5.0v ? p vrf 3.0v to 0v with t fall = 5s ? i o = 7ma . c out =220nf/ x5r ? v out < 0.4v -- -- 225 s
10 11030a?pmaac?13-sep-10 AT73C260 8. components list. table 8-1. AT73C260 external components list component name component type value / tol. reference reference r 1 , r 2 resistor 33 +/- 5% crg0402j33r r 3 resistor 10 +/- 5% crg0603j10r r 4 resistor 10k +/- 1% cpf0402f10ke1 r 5 resistor 100k +/- 1% cpf0603f100kc1 r 6 , r 7 resistor 22k +/- 5% crg0402j22k c 1 , c 2 ceramic capacitor cog 22pf +/- 20% c1005cog1h220j grm1555c1h220jz01 c 3 ceramic capacitor x5r 1f +/- 20% c1005x5r0j105k grm155r60j105ke19 c 4 ceramic capacitor x5r 220nf +/- 20% c1005x5r1c224kt grm155r60j224ke01 c 5 ceramic capacitor x5r 220nf +/- 20% c1005x5r1c224kt grm155r60j224ke01
11 11030a?pmaac?13-sep-10 AT73C260 9. functional description 9.1 AT73C260?s upstream and downstream ports this section relates to either upstream or downstream ports with digital, ic_usb1.0 or usb2.0 section 7 electrical characteristics. table 9-1 shows the configuration of the upstream and downstream ports based on pins 14, 15 and 16 voltages. ? 0 is when the pin is connected to gnd. ? 1 is when the pin is connected to h vcc . notes: 1. p vcc is set to 3.3v and external pull down resistors of 22k 5% are connected, one between pdp and gnd and the other between pdm and gnd. table 9-1. upstream and downstream ports m<2> pin 14 m<1> pin 15 m<0> pin 16 upstream port downstream port 0 0 0 digital ic_usb1.0 0 0 1 digital ic_usb1.0 0 1 0 digital ic_usb1.0 0 1 1 digital ic_usb1.0 1 0 0 not used not used 1 0 1 digital ic_usb1.0 1 1 0 section 7 ic_usb1.0 1 1 1 ic_usb1.0 section 7 (1) / ic_usb1.0
12 11030a?pmaac?13-sep-10 AT73C260 9.2 AT73C260 pull up and pull down resistors pull down resistors r pdp and r pdh values and behaviors comply with the ic_usb1.0 specifica - tion published by the usb-if. 9.2.1 AT73C260 upstream port connectivity (h vcc , h dp , h dm ): the host, ic_usb1.0 or usb2.0 section 7, is connected to the AT73C260?s upstream port. ? when in ic_usb 1.0 r pu2 is selected. ? when in usb2.0 section 7 r pu1 is selected. 9.2.2 AT73C260 downstream port connectivity (p vcc , p dp , p dm ): the peripheral, ic_usb1.0 or usb2.0 section 7, is connected to the AT73C260?s downstream port. ? an ic_usb1.0 peripheral is connected to the AT73C260?s downstream port. ? an usb2.0 section 7 peripheral is connected to the AT73C260?s downstream port with external pull down resistors as per precedent note (1) (see table 9-1 on page 11 ). figure 9-1. AT73C260 downstream and upstream ports sw5 rpdh sw6 hvcc pvcc hdm hdp pdm pdp gnd sw2 rpu2 sw1 rpu1 rpdp sw3 sw4
13 11030a?pmaac?13-sep-10 AT73C260 9.3 theory of operation 9.3.1 remote wake up the AT73C260 does not support remote wake up. 9.3.2 slew rate control when the AT73C260 drives an ic_usb bus section the output buffer on each line ( figure 9-2 ) drives the pin with a slew rate control to minimize radiated emi. figure 9-2. AT73C260 output buffer figure 9-3. AT73C260 output buffer slew rate note: see table 7-3 on page 7 for timing values. output buffers txic_dp txic_dm c t c t c t = 18pf t r 90% 10% t f 90% 10%
14 11030a?pmaac?13-sep-10 AT73C260 9.3.3 attach figure 9-4. AT73C260 attach sequence in the following paragraphs, two different attach sequences are described according the mode selected. mode vcc and mode s7_icc_tk are explained. 9.3.3.1 attach sequence ?mode vcc? the following sequence describes the AT73C260 with an ic_usb upstream connection and an ic_usb downstream connection ( mode vcc ). for hardware connection refers to ?mode: volt - age class converter: vcc? on page 34 . ?h vcc and p vcc are present and are in their dedicated voltage range. ?r pu1 is not used (sw1 always open). (for more information about switches, refers to figure 9-1 on page 12 ) ? before t 1 , r pdp and r pdh are connected. r pu2 is disconnected. (for more information about resistors, refers to figure 9-1 on page 12 ) ? t 1 : peripheral event. beyond t 1 , pdp is driven high by the ic_usb peripheral?s pull-up resistor. ? t 2 : AT73C260 event. the signal is above v ih . the AT73C260 verifies that the condition pdp is high lasts more than 200ns nominal. this information is passed to the AT73C260?s host side. ? t 3 : AT73C260 event. beyond t 3 , r pu2 (2k nominal) is connected while r pdp on hdp is disconnected. ? t 4 : host event. from t 4 the host drives the reset with se0. ? t 5 : AT73C260 event. it takes 40 ns nominal beyond t 4 for pdp to be driven low. ? t 6 : AT73C260 event. during reset the AT73C260 detects a se0 for more than 1s nominal. beyond t 6 both r pdh are disconnected. hdp pdp t 1 idle idle reset t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11
15 11030a?pmaac?13-sep-10 AT73C260 ? t 7 : host event. host stops driving se0. the AT73C260 with its 2k nominal resistor, pulls-up hdp. ? t 8 : AT73C260 event. the signal is above v ih .(on hdp) ? t 9 : AT73C260 event. 40ns nominal after t 8 . from t 9 , the AT73C260 drives high until v ih (on pdp) is reached plus 100ns nominal until t 11 . ? t 10 : AT73C260 event. between t 7 and t 10 . hdp is pulled-up with 2k nominal until v ih (on hdp) is reached plus 100ns. at t 10 r pu2 becomes 50k nominal. 9.3.3.2 attach sequence mode s7_icc_tk the following sequence describes the AT73C260 with an usb2.0 section 7 upstream connec - tion and an ic_usb downstream connection ( mode s7_icc_tk ). for hardware connection refers to ?mode: usb2.0 section 7 to ic_usb1.0 with pvcc fixed by pvrf: s7_icc_tk? on page 38 . ?h vcc = 3.3v and p vcc are present and are in their dedicated voltage range. ?r pu2 is not used (sw2 always open). r pdp are not used (sw3 and sw4 always open).(for more information about switches, refers to figure 9-1 on page 12 ) ? before t 1 , r pdh are connected. r pu2 is disconnected. (for more information about resistors, refers to figure 9-1 on page 12 ) ? t 1 : peripheral event. beyond t 1 , pdp is driven high by the ic_usb peripheral?s pull-up resistor. ? t 2 : AT73C260 event. the signal is above v ih . the AT73C260 verifies that the condition pdp is high lasts more than 200ns nominal. this information is passed to the AT73C260?s host side. ? t 3 : AT73C260 event. beyond t 3 , r pu1 1.2k nominal, is connected. ? t 4 : host event. from t 4 the host drives the reset with se0. ? t 5 : AT73C260 event. r pu1 becomes 2.2k nominal. it takes 40 ns nominal beyond t 4 for pdp to be driven low. ? t 6 : AT73C260 event. during reset the AT73C260 detects a se0 for more than 1s nominal. beyond t 6 both r pdh are disconnected. ? t 7 : host event. host stops driving se0. the AT73C260 with its 2k nominal resistor, pulls-up hdp. ? t 8 : AT73C260 event. the signal is above v ih .(on hdp)
16 11030a?pmaac?13-sep-10 AT73C260 ? t 9 : AT73C260 event. 40ns nominal after t 8 . from t 9 , the AT73C260 drives high until v ih (on pdp) is reached plus 100ns nominal until t 11 . ? t 10 : AT73C260 event. between t 7 and t 10 . hdp is pulled-up with 2.2k nominal until v ih (on hdp) is reached plus 100ns. at t 10 r pu1 becomes 1.2k nominal. 9.3.4 pvrf driving pvcc figure 9-5. AT73C260 pvrf driving pvcc when v bus , pin 4, is providing power to the usb uicc via the ldos, the voltage on p vcc (pin 12) is following the voltage on p vrf (pin 9). t start is mostly related to the capacitive load on p vcc and the strength of the ldo?s pmos. t start as mentioned in table 7-8 on page 9 is less than 50s. t stop is mostly related to the load on p vcc since the ldo?s pmos is off when starts t off . certain applications may require p vcc to fall below a minimum voltage in less than t off and guarantee a power on reset sequence in the usb uicc when p vcc is set again. for these applications an extra load, such as a resistor across p vcc and gnd in parallel with the usb uicc and the decoupling capacitor c5 may be required. as an example, for t off = 0.4ms, a decoupling capacitor c5 of 220nf and an usb uicc in standby (less than 100a) the extra resistor shall be less than 1k . pvrf pvcc 10% 90% t start t stop t off
17 11030a?pmaac?13-sep-10 AT73C260 9.3.5 reset signaling at the end of the reset signaling on AT73C260?s host side and peripheral sides the pulled up data line voltage has to reach v ih_min in less than t ddis , see figure 9-6 . if it is not the case, the host may see a disconnect condition. reset is forced during t2. if a 100k pull up resistor is used while the capacitive load is more than 20pf, the time constant is greater than 2s. to avoid any disconnect condition, the AT73C260 pulls up the appropriate data line during about one bit duration with extra strength making the disconnect condition unlikely. figure 9-6. AT73C260 reset signaling 9.3.6 resume signaling the AT73C260 supports resume signaling. the timings on ic_dp and ic_dm are those on hdp and hdm delayed by 40ns nominal. figure 9-7. AT73C260 resume signaling notes: 1. j state means that hdp = 1 and hdm = 0. 2. k state means that hdp = 0 and hdm = 1. 3. sof = start of frame v ih_min less than t ddis min (2s) ic_dp ic_dm reset signaling t1 t2 hdp hdm idle, j state the hub signals resume to the uicc by forcing a k state during t drsmdn ( 20ms) sof t drsmnd ( 20ms minimum) eop (two low speed bit time) one j state 3ms max
18 11030a?pmaac?13-sep-10 AT73C260 9.4 general description the AT73C260 covers four main functions: ? phy (described in section 9.4.3 on page 20 ) ? bridge (described in section 9.4.4 on page 30 ) ? ic_usb1.0 voltage class converter (described in section 9.4.5 on page 34 ) ? bridge with ldos for two specific applications (described in section 9.4.6 on page 36 ), and one extra function from many described as an example where the AT73C260 is an inter- chip phy in a digital implementation (fpga) of a peripheral. 9.4.1 application modes the following table 9-2 lists the applications and pin settings. notes: 1. 22k pull down on pins 10 and 11 2. pc with digital base band 3. token 4. m<2:0> code?100? is not used table 9-2. AT73C260 application modes (4) mode application m<2> pin 14 m<1> pin 15 m<0> pin 16 function phy_6_se0 digital six wires unidirectional dat_se0 to ic_usb1.0 0 0 0 phy phy_4_se0 digital four wires bidirectional dat_se0 to ic_usb1.0 0 0 1 phy phy_6_dpdm digital six wires unidirectional dp_dm to ic_usb1.0 0 1 0 phy phy_4_dpdm digital four wires bidirectional dp_dm to ic_usb1.0 0 1 1 phy phy_3_ulpi digital three wires bidirectional (dat, se0, oe_n) to ic_usb1.0 1 0 1 phy s7_icc usb2.0 section 7 without cable to ic_usb1.0 1 1 0 bridge s7_icc_dbb usb2.0 section 7 with cable to ic_usb1.0, ldos on vcc driven by the digital base band (2) 1 1 0 bridge with ldos s7_icc_tk usb2.0 section 7 with cable to ic_usb1.0, ldos on vcc fixed by pvrf (3) 1 1 0 bridge with ldos icc_s7 ic_usb1.0 to usb2.0 section 7 (1) 1 1 1 bridge vcc ic_usb1.0 to ic_usb1.0 1 1 1 voltage class converter
19 11030a?pmaac?13-sep-10 AT73C260 9.4.2 function descriptions 9.4.2.1 downstream port phy: a set of digital signals generated by an fpga or an asic with i/o powered by a first power sup - ply drive the AT73C260 which converts these signals into analog signals ic_dp and ic_dm as per ic_usb1.0 powered by a second power supply. 9.4.2.2 bridge: two cases are supported: usb2.0 section 7 to ic_usb1.0 and ic_usb1.0 to usb2.0 section 7. ? usb2.0 section 7 to ic_usb1.0 downstream d+ and d- signals drive the at73c 260 which converts t hese signals into analog signals ic_dp and ic_dm as per ic_usb1.0. ? ic_usb1.0 to usb2.0 section 7 downstream ic_usb1.0 signals drive the at73c2 60 which converts these signals into analog signals d+ and d- as per usb2.0 section 7. 9.4.2.3 voltage class converter: the following applications enable communications between an ic_usb1.0 compliant down - stream port with a first voltage class v 1 and an ic_usb1.0 compliant peripheral with a second voltage class v cc . the range of the supplies, respectively host and device, are: h vcc (1.55v - 3.6v) and p vcc (1.55v - 3.6v) 9.4.2.4 bridge with ldos: two cases are supported: one for pc with embedded digital base band and one for token. ? pc with embedded digital base band the AT73C260 provides up to 70ma from v bus to the uicc under the v cc required by the dbb. also the AT73C260 converts d+ and d- signals into analog signals ic_dp and ic_dm as per ic_usb1.0. ? token the AT73C260 provides up to 70ma from v bus to the uicc under v cc . this voltage is generated by p vcc ldo and set by an external resistor bridge supplied by 3.3v voltage reference (h vcc ). also the AT73C260 converts d+ and d- signal s into analog signals ic_dp and ic_dm as per ic_usb1.0.
20 11030a?pmaac?13-sep-10 AT73C260 9.4.3 downstream port phy in mobile applications, the usb uicc is handled by the user and special care should be taken in the esd protection on the downstream port facing the usb uicc. the AT73C260 downstream port is protected against 4kv esd. also, the host and the usb uicc may not be located on the same board with a flex connecting the two pcbs. the AT73C260 should be located next to the host. the flex is between the AT73C260?s downstream port and the usb uicc upstream port. the AT73C260 downstream port has slew rate control on both p dm and p dp to minimize the radiated emi. pins v bus and p vrf are connected to gnd and ldo outputs are isolated and in standby. 9.4.3.1 mode: digital six wires unidirectional dat_se0 to ic_usb1.0: phy_6_se0 description this application allows a host, asic or fpga, with the digital unidirectional philips pdiusbp11a (mode pin = 0) six wires interface to drive an ic_usb downstream port. figure 9-8. phy_6_se0 block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-3. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application phy_6_se0 0 0 0 digital six wires unidirectional dat_se0 to ic_usb1.0 table 9-4. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- supply by asic fpga i/o ring (1.55v to 3.6v) 2 tx_dat d-input -- unidirectional transmit data 3 tx_seo d-input -- unidirectional transmit single ended 0 4 vbus a-input -- not used and connected to ground 6 rx_dm d-output -- unidirectional receiving dm 7 rx_dp d-output -- unidirectional receiving dp 8 tx_enable_n d-input low tx enable n 9 pvrf a-input -- connected to ground 10 pdm d-i/o -- downstream port for usb device AT73C260 asic fpga ic_usb_1.0 dat_seo 6
21 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-9. AT73C260: phy - 6 wires dat_se0 to ic_usb1.0 - application diagram note: all external components are defined in component list table 8-1 on page 10 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-power -- same as peripheral?s power (1.8v or 3v typical) 13 rx_rcv d-output -- unidirectional receiving rcv 14, 15, 16 m<2:0> d-inputs low connected to ground table 9-4. AT73C260 pin description and configuration pin number pin name i/o type polarity function c 4 hvcc gnd 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> c 5 pvcc usb uicc ic_dm ic_dp v cc iso/iec 7816-3 tx_dat rx_rcv tx_se0 rx_dm rx_dp tx_enable_n asic/fpga : 6 wires dat_se0 utmi digital wrapper tx_dat rx_rcv tx_se0 rx_dm rx_dp tx_enable_n
22 11030a?pmaac?13-sep-10 AT73C260 9.4.3.2 mode: digital four wires bidirectional dat_se0 to ic_usb1.0: phy_4_se0 description this application allows a host, asic or fpga, with the digital bidirectional utmifs, dat_se0, four wires interface to drive an ic_usb downstream port. figure 9-10. phy_4_se0 block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-5. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application phy_4_se0 0 0 h vcc digital four wires bidirectional dat_se0 to ic_usb1.0 table 9-6. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- supply by asic fpga i/o ring (1.55v to 3.6v) 2 tx_dat/rx_dp d-i/o -- bidirectional rx_dp/tx_data 3 tx_se0/rx_dm d-i/o -- bidirectional rx_dm/tx_single ended 0 4 vbus a-input -- not used and connected to ground 6 hdmo d-output hiz not connected 7 hdpo d-output hiz not connected 8 tx_enable_n d-input low tx enable n 9 pvrf a-input -- connected to ground 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-power -- same as peripheral?s power (1.8v or 3v typical) 13 rx_rcv d-output -- unidirectional receiving rcv 14, 15 m<2:1> d-inputs low connected to ground 16 m<0> d-input high connected to h vcc AT73C260 asic fpga ic_usb_1.0 4 dat_seo
23 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-11. AT73C260: phy - 4 wires dat_se0 to ic_usb1.0 - application diagram note: all external components are defined in component list table 8-1 on page 10 c 4 hvcc gnd 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> nc nc hvcc c 5 pvcc usb uicc ic_dm ic_dp v cc iso/iec 7816-3 tx_dat/rx_dp rx_rcv tx_se0/rx_dm tx_enable_n tx_dat rx_rcv tx_se0 rx_dm rx_dp tx_enable_n asic/fpga : 4 wires dat_se0 utmi digital wrapper
24 11030a?pmaac?13-sep-10 AT73C260 9.4.3.3 mode: digital six wires unidirectional dp_dm to ic_usb1.0: phy_6_dpdm description this application allows a host, asic or fpga, with the digital unidirectional philips pdiusbp11a (mode pin = 1) six wires interface to drive an ic_usb downstream port. figure 9-12. phy_6_dpdm block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-7. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application phy_6_dpdm 0 h vcc 0 digital six wires unidirectional dp_dm to ic_usb1.0 table 9-8. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- supply by asic fpga i/o ring (1.55v to 3.6v) 2 tx_dp d-input -- unidirectional tx dp 3 tx_dm d-input -- unidirectional tx dm 4 vbus a-input -- not used and connected to ground 6 rx_dm d-output -- unidirectional rx dm 7 rx_dp d-output -- unidirectional rx dp 8 tx_enable_n d-input low tx enable n 9 pvrf a-input -- connected to ground 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-power -- same as peripheral?s power (1.8v or 3v typical) 13 rx_rcv d-output -- unidirectional receiving rcv 14 m<2> d-input low connected to ground 15 m<1> d-input high connected to h vcc 16 m<0> d-input low connected to ground AT73C260 asic fpga ic_usb_1.0 6 dp_dm
25 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-13. AT73C260: phy - 6 wires dp_ dm to ic_usb1.0 - application diagram note: all external components are defined in component list table 8-1 on page 10 c 4 hvcc gnd 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> hvcc c 5 pvcc usb uicc ic_dm ic_dp v cc iso/iec 7816-3 tx_dp rx_rcv tx_dm tx_enable_n tx_dat rx_rcv tx_se0 rx_dm rx_dp tx_enable_n asic/fpga : 6 wires dp_dm utmi digital wrapper rx_dp rx_dm
26 11030a?pmaac?13-sep-10 AT73C260 9.4.3.4 mode: digital four wires bidirectional dp_dm to ic_usb1.0: phy_4_dpdm description this application allows a host, asic or fpga, with the digital bidirectional utmifs, dp_dm, four wires interface to drive an ic_usb downstream port. figure 9-14. phy_4_dpdm block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-9. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application phy_4_dpdm 0 h vcc h vcc digital four wires bidirectional dp_dm to ic_usb1.0 table 9-10. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- supply by asic fpga i/o ring (1.55v to 3.6v) 2 tx_dp/rx_dp d-i/o -- bidirectional tx_dp/dx_dp 3 tx_dm/rx_dm d-i/o -- bidirectional tx_dm/dx_dm 4 vbus a-input -- not used and connected to ground 6 hdmo d-output hiz not connected 7 hdpo d-output hiz not connected 8 tx_enable_n d-input low tx enable n 9 pvrf a-input -- connected to ground 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-power -- same as peripheral?s power (1.8v or 3v typical) 13 rx_rcv d-output -- unidirectional receiving rcv 14 m<2> d-input low connected to ground 15,16 m<1:0> d-inputs high connected to h vcc AT73C260 asic fpga ic_usb_1.0 4 dp_dm
27 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-15. AT73C260: phy - 4 wires dp_ dm to ic_usb1.0 - application diagram note: all external components are defined in component list table 8-1 on page 10 c 4 hvcc gnd 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> nc nc hvcc c 5 pvcc usb uicc ic_dm ic_dp v cc iso/iec 7816-3 tx_dp/rx_dp rx_rcv tx_dm/rx_dm tx_enable_n tx_dat rx_rcv tx_se0 rx_dm rx_dp tx_enable_n asic/fpga : 4 wires dp_dm utmi digital wrapper
28 11030a?pmaac?13-sep-10 AT73C260 9.4.3.5 mode: digital three wires bidirectional (dat, se0, oe_n) to ic_usb1.0: phy_3_ulpi description this application allows a host, asic or fpga, with the digital bidirectional ulpi serial support, dat, se0, and oe_n, three wires interface to drive an ic_usb downstream port. figure 9-16. phy_3_ulpi block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-11. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application phy_3_ulpi h vcc 0 h vcc digital three wires bidirectional dat, se0, oe_n to ic_usb1.0 table 9-12. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- supply by asic fpga i/o ring (1.55v to 3.6v) 2 rx_rcv/tx_dat d-i/o -- bidirectional rx_rcv / tx_data 3 rx_se0/tx_se0 d-i/o -- bidirectional rx_se0/tx_se0 4 vbus a-input -- not used and connected to ground 6 hdmo d-output hiz not connected 7 hdpo d-output hiz not connected 8 tx_enable_n d-input low tx enable n 9 pvrf a-input -- connected to ground 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-power -- same as peripheral?s power (1.8v or 3v typical) 13 rcv d-output hiz not connected 14 m<2> d-input high connected to h vcc 15 m<1> d-inputs low connected to ground 16 m<0> d-inputs high connected to h vcc AT73C260 asic fpga ic_usb_1.0 3 ulpi
29 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-17. AT73C260: phy - 3 wires dat, se0, oe_n to ic_usb1.0 - application diagram note: all external components are defined in component list table 8-1 on page 10 c 4 hvcc gnd 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> nc nc nc hvcc c 5 pvcc usb uicc ic_dm ic_dp v cc iso/iec 7816-3 rx_rcv/tx_dat rx_se0/tx_se0 tx_enable_n tx_dat rx_rcv tx_se0 rx_dm rx_dp tx_enable_n asic/fpga : 3 wires dat, se0, oe_n utmi digital wrapper
30 11030a?pmaac?13-sep-10 AT73C260 9.4.4 bridge pins v bus and p vrf are connected to gnd and ldo outputs are isolated and in standby. pin oe_n is connected to h vcc . the following applications enable communications between. ? s7_icc : an usb2.0 section 7 compliant downstream port and an ic_usb1.0 compliant peripheral ? icc_s7 : an ic_usb1.0 compliant downstream port and an usb2.0 section 7 compliant peripheral 9.4.4.1 mode: usb2.0 section 7 downstream port to ic_usb1.0 peripheral: s7_icc description this application establishes a communication pa th between an usb2.0 section 7 downstream port and an ic_usb peripheral. an external 3.3v voltage source is applied on h vcc . AT73C260?s d+ and d- input pins are com - pliant with usb2.0 core specification. this application is particularly well suited for mobile devices where the host may not have an ic_usb1.0 downstream port. figure 9-18. s7_icc block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-13. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application s7_icc h vcc h vcc 0 usb2.0 section 7 downstream port to ic_usb1.0 peripheral table 9-14. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- supplied by host at 3.3v 2 d+ d-i/o -- bidirectional d+ 3 d- d-i/o -- bidirectional d- 4 vbus a-input -- not used and connected to ground 6 hdmo d-output hiz not connected 7 hdpo d-output hiz not connected 8 oe_n d-input high connected to h vcc AT73C260 ic_usb_1.0 usb 2.0 section 7
31 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-19. AT73C260: bridge - usb2.0 section 7 downstream port to ic_usb1.0 -application diagram note: all external components are defined in component list table 8-1 on page 10 9 pvrf a-input -- connected to ground 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-power -- same as peripheral?s power (1.8v or 3v typical) 13 rcv d-output hiz not connected 14 m<2> d-input high connected to h vcc 15 m<1> d-inputs high connected to h vcc 16 m<0> d-inputs low connected to ground table 9-14. AT73C260 pin description and configuration pin number pin name i/o type polarity function c 4 hvcc d + d - gnd c 5 pvcc usb uicc ic_dm ic_dp v cc iso/iec 7816-3 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> nc nc nc hvcc hvcc
32 11030a?pmaac?13-sep-10 AT73C260 9.4.4.2 mode: ic_usb1.0 downstream port to usb2.0 section 7 peripheral: icc_s7 description this application establishes a communication path between an ic_usb1.0 downstream port and an usb2.0 section 7 peripheral. figure 9-20. icc_s7 block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-15. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application icc_s7 h vcc h vcc h vcc ic_usb1.0 downstream port to usb2.0 section 7 peripheral table 9-16. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- same as host i/o ring power (1.8v to 3v typical) 2 ic_dp d-i/o -- bidirectional ic_dp 3 ic_dm d-i/o -- bidirectional ic_dm 4 vbus a-input -- not used and connected to ground 6 hdmo d-output hiz not connected 7 hdpo d-output hiz not connected 8 oe_n d-input high connected to h vcc 9 pvrf a-input -- connected to ground 10 d- d-i/o -- downstream port for usb device 11 d+ d-i/o -- downstream port for usb device 12 pvcc a-power -- supplied at 3.3v 13 rcv d-output hiz not connected 14 m<2> d-input high connected to h vcc 15 m<1> d-inputs high connected to h vcc 16 m<0> d-inputs high connected to h vcc AT73C260 ic_usb_1.0 usb 2.0 c/asic section 7
33 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-21. AT73C260: bridge - ic_usb1.0 downstream port to usb2.0 section 7 - application diagram note: r 6 and r 7 are defined in component list table 8-1 on page 10 c 4 ic_dp ic_dm gnd c 5 pvcc d - d + 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> nc nc nc r 6 r 7 h vcc h vcc h vcc
34 11030a?pmaac?13-sep-10 AT73C260 9.4.5 mode: voltage class converter: vcc description pins v bus and p vrf are connected to gnd and ldo outputs are isolated and in standby. pin oe_n is connected to h vcc . the following applications enable communications between an ic_usb1.0 compliant down - stream port with a first voltage class h vcc and an ic_usb1.0 compliant peripheral with a second voltage class p vcc . figure 9-22. voltage class converter block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-17. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application vcc h vcc h vcc h vcc ic_usb1.0 to ic_usb1.0 voltage class converter table 9-18. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- same as host i/o ring power (1.8v to 3v typical) 2 ic_dp d-i/o -- bidirectional ic_dp 3 ic_dm d-i/o -- bidirectional ic_dm 4 vbus a-input -- connected to ground 6 hdmo d-output hiz not connected 7 hdpo d-output hiz not connected 8 oe_n d-input high connected to h vcc 9 pvrf a-input -- connected to ground 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-power -- same as peripheral?s power (1.8v or 3v typical) 13 rcv d-output hiz not connected 14 m<2> d-input high connected to h vcc 15 m<1> d-inputs high connected to h vcc 16 m<0> d-inputs high connected to h vcc AT73C260 ic_usb_1.0 asic ic_usb_1.0
35 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-23. AT73C260: voltage class converter - ic_usb1.0 to ic_usb1.0 - application diagram note: all external components are defined in component list table 8-1 on page 10 c 4 ic_dp ic_dm gnd c 5 pvcc hvcc usb uicc ic_dm ic_dp v cc iso/iec 7816-3 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> nc nc nc hvcc hvcc
36 11030a?pmaac?13-sep-10 AT73C260 9.4.6 bridge with ldos ldos are enabled. AT73C260?s pin v bus is connected to the usb signal v bus through a low pass filter. 9.4.6.1 mode: pc?s usb2.0 section 7 to ic_usb1.0 with vcc driven by the dbb: s7_icc_dbb description the pc?s digital base band may not provide enough power to a usb uicc with mass storage. the v bus power supply voltage will make available t hat extra power, up to 70ma, through the AT73C260?s ldo if needed by the usb uicc. the pc?s digital base band supplies on pin 9 the power sequence required by etsi. the AT73C260 buffers the signal on p vrf to p vcc . p vcc sources power from v bus to v cc . on the host side h vcc generates 3.3v from v bus . figure 9-24. s7_icc_dbb block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-19. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application s7_icc_dbb h vcc h vcc 0 pc?s usb2.0 section 7 to ic_usb1.0 with v cc driven by dbb table 9-20. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-output -- delivered by AT73C260 from vbus at 3.3v 2 d+ d-i/o -- bidirectional d + 3 d- d-i/o -- bidirectional d - 4 vbus a-input -- supplied by usb power line 6 hdmo d-output hiz not connected 7 hdpo d-output hiz not connected 8 oe_n d-input high connected to h vcc 9 pvrf a-input -- control by digital base band AT73C260 phone c/asic ic_usb_1.0 usb 2.0 dbb iso7816 v bus p vrf p vcc
37 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-25. AT73C260: bridge with ldo - usb2.0 section 7 to ic_usb1.0 with v cc driven by dbb - application diagram notes: 1. p vcc ldo regulator is compliant with sim fta 27.17.2.1 tests series. 2. all external components are defined in component list table 8-1 on page 10 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-output -- delivered by AT73C260 from vbus and control by dbb 13 rcv d-output hiz not connected 14 m<2> d-input high connected to h vcc 15 m<1> d-inputs high connected to h vcc 16 m<0> d-inputs low connected to ground table 9-20. AT73C260 pin description and configuration pin number pin name i/o type polarity function c 4 gnd c 5 usb uicc ic_dm ic_dp v cc iso/iec 7816-3 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 8 6 4 7 rcv oe_n hdmo hdpo 16 15 gnd 14 m<2> p vrf v bus vref 3.3volt m<1> m<0> nc nc nc digital base band i/o rst clk 2 3 9 d + r 1 c 1 d - c 2 r 2 v bus r 3 c 3 hvcc hdp hdm hvcc hvcc
38 11030a?pmaac?13-sep-10 AT73C260 9.4.6.2 mode: usb2.0 section 7 to ic_usb1.0 with pvcc fixed by pvrf: s7_icc_tk description this is a token application where an usb uicc is connected to an usb2.0 section 7 down - stream port. the AT73C260?s ldos supply h vcc set at 3.3v and p vcc set at the power supply voltage required by the usb uicc. this application establishes a communication path between a usb2.0 section 7 downstream port and the usb uicc?s. the power to the usb uicc is provided by v bus using an ldo able to source up to 70ma. this is the typical electrical schematic for a usb uicc used in a usb token to be connected to a usb2.0 series a receptacle. the voltage divider r 4 /r 5 generates for example 3.0v buffered by the ldo to the downstream side of the transceiver and to the usb uicc p vcc . this set up allows passing usb cv tests to the usb uicc under tests. figure 9-26. s7_icc_tk block diagram (token application) hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-21. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application s7_icc_tk h vcc h vcc 0 usb2.0 section 7 to ic_usb1.0 with p vcc fixed by p vrf table 9-22. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-output -- delivered by AT73C260 from vbus at 3.3v 2 d+ d-i/o -- bidirectional d + 3 d- d-i/o -- bidirectional d - 4 vbus a-input -- supplied by usb power line 6 hdmo d-output hiz not connected 7 hdpo d-output hiz not connected AT73C260 ic_usb_1.0 usb 2.0 v bus p vrf hvcc=3.3v p vcc
39 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-27. AT73C260: bridge with ldo - usb2.0 section 7 to ic_usb1.0 with v cc fixed by p vrf - application diagram notes: 1. p vcc ldo regulator is compliant with sim fta 27.17.2.1 tests series. 2. all external components are defined in component list table 8-1 on page 10 8 oe_n d-input high connected to h vcc 9 pvrf a-input -- fixed by external resistor bridge divider 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-output -- delivered by AT73C260 from vbus according external resistor ratio 13 rcv d-output hiz not connected 14 m<2> d-input high connected to h vcc 15 m<1> d-inputs high connected to h vcc 16 m<0> d-inputs low connected to ground table 9-22. AT73C260 pin description and configuration pin number pin name i/o type polarity function gnd c 5 usb uicc ic_dm ic_dp v cc iso/iec 7816-3 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 8 6 4 7 rcv oe_n hdmo hdpo 16 15 gnd 14 m<2> p vrf v bus vref 3.3volt m<1> m<0> nc nc nc 2 3 9 d + r 1 c 1 d - c 2 r 2 v bus r 3 c 3 hdp hdm from host usb2.0 section 7 with cable r 5 r 4 c 4 hvcc p vrf = p vcc = h vcc * r 5 /(r 5 +r 4 ) hvcc hvcc
40 11030a?pmaac?13-sep-10 AT73C260 3. external resistors shall be in the following range: 100k < r4 + r5 < 330k in order to mini - mize current consumption and to reach a good accuracy on p vcc . the bias current of p vrf follower is less than +/-100na.
41 11030a?pmaac?13-sep-10 AT73C260 9.4.7 example of an extra function for an fpga implementation of a usb device, there is a need for an upstream ic_usb 1.0 phy. for this requirement the AT73C260 product can be configured as described below. pins v bus and p vrf are connected to gnd and ldo outputs are isolated and in standby. 9.4.7.1 mode: digital six wires unidirectional dat_se0 to ic_usb1.0 upstream: extra function description this application allows a peripheral based on an asic or an fpga with the digital unidirectional six wires interface to be connected to an ic_usb 1.0 downstream port. here below, an example is shown. other digital interfaces are compatible with this upstream ic_usb 1.0 port. figure 9-28. phy_6_se0 block diagram hardware configuration in the following tables, the pin and the hardware configuration are described. table 9-23. AT73C260 hardware configuration mode m<2> pin 14 m<1> pin 15 m<0> pin 16 application extra mode (as an example) 0 0 0 digital six wires unidirectional dat_se0 to ic_usb1.0 upstream table 9-24. AT73C260 pin description and configuration pin number pin name i/o type polarity function 1 hvcc a-power -- same as peripheral i/o ring (1.55v to 3.6v typical) 2 tx_dat d-input -- unidirectional transmit data 3 tx_seo d-input -- unidirectional transmit single ended 0 4 vbus a-input -- not used and connected to ground 6 rx_dm d-output -- unidirectional receiving dm 7 rx_dp d-output -- unidirectional receiving dp 8 tx_enable_n d-input low tx enable n AT73C260 asic fpga ic_usb_1.0 6 host pull-up control dat_seo
42 11030a?pmaac?13-sep-10 AT73C260 application diagram in the following figure, the hardware configuration is described. figure 9-29. AT73C260: extra mode - phy of a 6-wire fpga peripheral implementation - application diagram notes: 1. all external components are defined in component list table 8-1 on page 10 2. in upstream port configuration, the software must drive the r ext pull-up resistor. 9 pvrf a-input -- connected to ground 10 pdm d-i/o -- downstream port for usb device 11 pdp d-i/o -- downstream port for usb device 12 pvcc a-power -- same power as host vcc (1.8 or 3v typical) 13 rx_rcv d-output -- unidirectional receiving rcv 14, 15, 16 m<2:0> d-inputs low connected to ground table 9-24. AT73C260 pin description and configuration pin number pin name i/o type polarity function c 4 hvcc gnd 13 h vcc p vcc pdm 112 pdp 10 11 AT73C260 5 2 3 8 6 4 7 hdp rcv hdm oe_n hdmo hdpo 16 15 gnd 14 m<2> 9 p vrf v bus vref 3.3volt m<1> m<0> hvcc c 5 pvcc host ic_dm ic_dp v cc r ext pvcc pull-up control tx_dp rx_rcv tx_dm tx_enable_n tx_dat rx_rcv tx_se0 rx_dm rx_dp tx_enable_n pull-up control asic/fpga : peripheral 6 wires dat_se0 utmi digital wrapper rx_dp rx_dm
43 11030a?pmaac?13-sep-10 AT73C260 10. package information figure 10-1. mechanical package drawing for 16-lead quad flat no lead package note: all the dimensions are in mm
44 11030a?pmaac?13-sep-10 AT73C260 11. ordering information table 11-1. ordering information ordering code package package type temperature operating range AT73C260 qfn16 3 x 3 mm green -40c to +85c
45 11030a?pmaac?13-sep-10 AT73C260 12. revision history doc. rev date comments change request ref. 11030a 13-sep-10 first revision
46 11030a?pmaac?13-sep-10 AT73C260
i 11030a?pmaac?13-sep-10 AT73C260 1 block diagram .......................................................................................... 2 2 package and pinout ................................................................................. 3 3 pin description ......................................................................................... 4 4 absolute maximum ratings .................................................................... 5 5 recommended operating conditions .................................................... 5 6 power dissipation ratings ...................................................................... 5 7 electrical characteristics ........................................................................ 6 7.1 i/os dc characteristics referred to hvcc ...............................................................6 7.2 i/os dc characteristics referred to pvcc ...............................................................6 7.3 timing characteristics table .....................................................................................7 7.4 vbus supply characteristics ....................................................................................7 7.5 hvcc and pvcc supplies characteristics ...............................................................8 8 components list. ................................................................................... 10 9 functional description .......................................................................... 11 9.1 AT73C260?s upstream and downstream ports .......................................................11 9.2 AT73C260 pull up and pull down resistors ...........................................................12 9.3 theory of operation ................................................................................................13 9.4 general description .................................................................................................18 10 package information .............................................................................. 43 11 ordering information ............................................................................. 44 12 revision history ..................................................................................... 45
ii 11030a?pmaac?13-sep-10 AT73C260
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